1. Technical Field
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to a system and method for modeling metastability decay through latches in an integrated circuit model.
2. Description of Related Art
In physical hardware integrated circuit devices, metastability is a problem that occurs in elements, e.g., flip-flops, latches, and the like, of the integrated circuit device when a data or control input is changing at the instant of a clock pulse. The result is that the output of the integrated circuit element may behave unpredictably, taking many times longer than normal to settle to its correct state or even oscillating several times before settling. In an integrated circuit device, such problems may cause corruption of data as well as other problems.
In many cases, metastability in integrated circuit devices can be avoided by ensuring that the data and control inputs are held constant for specified periods of time before and after the clock pulse. These periods of time are referred to as the setup time and the hold time, respectively. These times are specified in the data sheet for the integrated circuit device and are typically between a few nanoseconds and a few hundred picoseconds for modern integrated circuit devices.
Unfortunately, it is not always possible to meet the setup and hold time criteria because the integrated circuit element may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit.
One technique for suppressing metastability is to connect two or more integrated circuit elements, e.g., flip-flops or latches, in a chain so that the output of each one feeds the data input of the next, and all of the integrated circuit elements share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero. For example, an integrated circuit element which attains a metastable value will assume an indeterminate value, i.e. neither a logic 0 or logic 1. This indeterminate value will be overwritten or decay to a random value, i.e. a logic 0 or logic 1, over time and/or through the use of additional integrated circuit elements provided in a chain, as mentioned above. Hence, there are two ways a metastable generated indeterminate value can be reduced to a random value—1) by using additional synchronization latches connected in a chain, or 2) by time.
In simulation of integrated circuit designs, while it is possible to model the metastability of a latch by using an indeterminate value, there currently is no ability to model the decay of such a metastable indeterminate value to a random value. In other words, during simulation of an integrated circuit design model, an indeterminate value does not decay as it would in the real physical hardware of the integrated circuit device. Thus, the only way to treat such indeterminate values in the simulation is to overwrite them with other logic in the simulation so that downstream logic of the metastable element does not see the indeterminate value. This, however, does not accurately represent the actual operation of the real physical hardware when the integrated circuit device is fabricated.